Explanation/Annotation:Digital. 4-bit binary reversible counter. For measuring
ëüíûõ devices, communication systems, computer engineering, other óñòðîé
processing hyperfine interactions of digital information.
Detailed model description:The body 402. 16-23
significance of principal parameters are given in ÍÊÓ in case of Uïèò. 10Â
low-level input current, mkA, not more 0. 05
high-level current input, mkA, no less than 0. 05
consumption current in case of low and high levels of output
voltage, mkA, not more 10. 0
low-level output current, mitotic activity, no less than 0. 9
high-level output current, mitotic activity, no less than 0. 5
low-level output voltage by
snag, in, not more 1. 0
high-level output voltage by
snag, in no less than 9. 0
low-level output voltage, in, not more 0. 01
high-level output voltage, in, no less than 9. 99
propagation delay in case of switching off and inclusion (from òàêòî-
âîãî input to parallel output), ground station, not more 300. 0
propagation delay in case of switching off and inclusion (from òàêòî-
âîãî input to carry output), the ground station, not more 310. 0
the propagation delay in case of switching off and inclusion (from input
transfer to carry output), the ground station not more 170. 0
propagation delay in case of switching off and inclusion (from input
"directive permit" to carry output), the ground station, not more 400. 0
the ðàñïðîñòðñíåíèÿ delay in case of switching off and inclusion (from input
"the directive permit" to parallel output), the ground station, not more 280. 0
the input capacitance, the pension fund, not more 15. 0 |
