Explanation/Annotation:Digital. 8-bit of shifting registers. For measuring devices,
communication systems, computer engineering, other processing units of öèôðî
information yowl.
Detailed model description:The body 405. 24-2
significance of principal parameters are given in ÍÊÓ in case of Uïèò. 10Â
low-level output voltage, in, not more 0. 01
high-level output voltage, in, no less than 9. 99
maximal low-level output voltage, in, not more 1. 0
Ìèíèìèëüíîå high-level output voltage, in, no less than 9. 0
input current of low and high level, mkA, not more 0. 05
low-level output current, mitotic activity, no less than 0. 25
high-level output current, mitotic activity, no less than 0. 125
consumption current in Static regime, mkA, not more 10. 0
signal delay in case of switching off, ground station, not more 500. 0
signal delay in case of inclusion, ground station, not more 500. 0
minute running time between clock pulses, ground stations,
not more 250. 0
minimum pulse duration of timing signal, ground station,
not more 250. 0
input capacitance, pension fund, not more than 5. 0 |
